Aspects of the present invention relate to a multi-level interconnect apparatus.
Currently, there is an ongoing effort to provide servers and other computing devices that use multi-chip modules (MCM's) with the ability to exhibit improved module performance. Improvements in module performance may be manifested in increased on-module memory, increased and improved communications functions and the presence of faster processor cores with greater capacity. These exemplary module performance improvements generally require increased MCM module circuit densities and this, in turn, requires that internal processing capacities expand along with continual growth in capacities of input/output (I/O) buses (i.e., Gx, SMP, PCIe, Memory, etc. buses).
Bandwidth of a given I/O bus is a product of a width and operating frequency of the I/O bus. As such, two traditional options to meet increased bus requirements have included increased bus frequency or increased bus width (i.e., increased contact count). Increasing the bus frequency to meet growth requirements is limited by several physical design factors, which include line length from driver to receiver and impedance changes through a module substrate, a land grid array (LGA), PCB vias and PCB line traces into a second interface for a receiving device. Meanwhile, the introduction of multiple interconnects and/or interfaces can significantly limit bus frequencies. Also, increasing I/O bus width by adding additional contacts drives contact pitch or spacing, line length, PCB (i.e., mother board) real estate and system packaging trade-offs. Increasing real estate (i.e., total substrate size) to accommodate additional contacts may further limit bus frequencies due to longer line lengths and insignificantly improves bandwidth. By contrast, reducing contact pitch to increase bandwidth increases signal coupling, which drives cross-talk and also limits bus frequencies.
Therefore, MCM assemblies experience a trade-off of increased size and reduced contact pitch to accommodate increased I/O. Both of these directions limit bus frequencies and may actually limit bus bandwidths.